Monday, February 21, 2011


Followup to my previous post, related to Kaveh's comment. This post describes how I set up HDMI TX and RX.
To test HDMI TX and RX, I loaded the HDMI switch example from Xilinx App Note 495. Loaded Top-level files dvi_demo.v and dvi_demo.ucf into ISE WebPACK, along with all the lower-level modules they require. Everything is in from Xilinx.
Board configuration:
JP6&JP7 in: link SCL/SDA between TX&RX.
JP11 in: boot from USB stick.
JP5 in: Enable J1 HDMI input.
Connected J2 to display, J3 to source (J1 sometimes works as well).
I load dvi_demo.bit from a USB stick - takes about 30 seconds each time.
Tested with a Samsung TV and DirecTV box and Samsung BluRay.
The LED's show that RX is sync'ing with the signal and the display shows up on the TV. Tried several channels at different resolutions (no 1080p ones available). Sometimes had to unplug and replug the HDMI cables to get things to sync up. Just video, no audio passing through yet for some reason.
So that's my progress so far.


Unknown said...

I made it somehow working too. The problem was the I2C connection between J2 and J3. Although we connect them by inserting jumpers JP6 and JP7, FPGA shorts them to ground. Because “TMDS-RX-SCL”, “TMDS-RX-SDA”, “TMDS-TX-SCL”, “TMDS-RT-SDA” are connected to FPGA pins but are not used in the design. By default, FPGA makes unused pins pulled to ground. There are two solutions: 1- to change the default setting so that unused pins are float, 2- to define these pins as input in the design. I used the second solution.
Now my problem is that it is too noisy. Seems like the receiver PLL doesn’t lock properly.


Joe Rothweiler said...

Good catch!! I thought the i2S signals looked flakey on the scope, but had not figured out why.

Unknown said...

Hi All,

I got some problems when i try to run the dvi_demo. I had included the dvi_demo.ucf but once i click to open the Timing Constraints interface, it shows three dialog box which show "The clock net dvi_rx0/rxclk and dvi_rx1/rxclk for Period constraint TS_DVI_CLOCK0/TS_DVI_CLOCK1 is not valid".

Even i ignore this error i can't see any observations on the LCD display (out) with my video source (in) after i programed dvi_demo.bit to the Atlys board through JTAG.

i had followed ur instruction on connecting the Jumper but still can't work.

Can anyone please help on it?

Joe Rothweiler said...

Chun Yin,
Regarding the clock net error: My understanding is that the -2 speed grade chip used in the Atlys can't handle some of the higher HDMI clock rates (See table 1 of XAPP 495). I changed the 2 TIMESPEC lines at the top of the ucf file from 100 to 95 MHz and that got rid of the error messages.
Only other thing I can suggest is try multiple sources and displays. Some seem to work, some don't.

hapv said...
This comment has been removed by the author.
hapv said...

HI all,
I inserted jumpers JP6 and JP7 and defined TMDS-RX-SCL,TMDS-RX-SDA, TMDS-TX-SCL as input of project but when i connect ATLYS board to HDMI port of my Laptop and LCD monitor, LED status didn't lighted, i thinks i2c interface is wrong, could you help me? thank you very much!

Joe Rothweiler said...

One idea is to try using a monitor with a DVI input, and an HDMI-to-DVI cable between the Atlys and the monitor. I've found that several devices won't talk to an HDMI device when the Atlys is in between, but they will send video (no audio) to DVI. I suspect it has something to do with the user restrictions built into the HDMI spec, but I haven't really investigated the problem.