Lattic iCEcube2 on Debian

I recently started looking at Lattice chips for a project that needs a fairly small FPGA. They have small devices that are significantly lower in cost than the larger Xilinx Spartan chips I've used in the past. To explore further, I ordered the ICE40HX1K eval board ($22) and downloaded the free iCEcube2 IDE for my Debian stable(Jessie) 64-bit PC.
The first try at installing the IDE hit issues:
 error while loading shared libraries: libXext.so.6: cannot open shared object file: No such file or directory
The library is installed, so obviously the IDE wants the 32-bit version. I haven't tried to work with 32-bit stuff since Debian went to the multiarch approach, so that led to a new learning experience. Previously one would install ia32 versions of the needed libraries. After a bit of googling, I found that the current approach is (as root, or using sudo):
dpkg --add-architecture i386 # Include 32-bit stuff
apt-get update  # Add in the lists of 32-bit packages.
apt-file search libXext.so.6 # Find out what package I need - libxext6 in this case.
apt-get install libxext6:i386 # Add the 32-bit version of thepackage.
Now, the install fails because it's missing libpng12.so.0, so repeat the apt-file search and apt-get install steps for that. In Total I ended up installing  libpng12-0:i386, libsm6:i386, libxi6:i386, libxrender1:i386, libxrandr2:i386, libxfixes3:i386, libxcursor1:i386, libxinerama1:i386, libfreetype6:i386, libfontconfig1:i386, libglib2.0-0:i386.
With that, iCEcube2 installs and runs.

Now I can start playing with the eval board when it shows up.

Notes:

hackaday.io/project/6592-dipsy/log/24272-installing-icecube-2-on-ubuntu-14042-lts  Pointed me in the right direction to complete the install. Their Dipsy project uses the Lattice chip, and looks interesting.

Parallel port jtag

I've been using a homebrew version of the Xilinx DLC5 parallel port jtag adapter for programming my fpga boards. The DLC5 is no longer supported by Xilinx, but some Linux jtag programmers still support it.
Recently I moved to a new PC, and my DLC5 hack no longer works with that parallel port. I can see on the scope that the right pins are moving, but the chip won't program. I suspect that either the rise and fall times are too slow, or there's noise on the signal lines.
Anyway, I had a sample of the SiLabs si8663 digital isolator, so I decided it's time to build a new interface. The Si8663 is a hex isolator (3 signals each direction), that's spec'ed to operate up to 150 Mbps bit rate (WAY more than needed for this app). Another neat feature is that the drivers on each side work from 2.5 to 5.5 volts, providing a level shifter at no extra charge.
Board is available on OshPark (www.oshpark.com) for anyone interested. Project name is "isopartag 140513". Circuit's simple: chip + 4 bypass caps on the bottom. The design includes resistors to tap power from unused pins of the parallel port, but they haven't been added yet, to that feature is untested. For now I just tap 5 volts from an unused keyboard or mouse port.
Caution:The Si8663 comes in two versions: a wide body for safety isolation, and a narrow body intended more for electrical noise isolation. I'm using the narrow version, and the board is not designed with wide separation between the input and output sides. In other words, this design is for low voltages only, don't use it where safety is an issue.

Xilinx Spartan-3 I/O timing

Working on updating the MHZ100Q project, and one significant design issue is I/O delay. To review, the Xilinx Spartan-3A FPGA generates a 100MHz clock using an internal DCM block, and this clock drives an external 100MHz A/D converter. The total delays through the output buffer, A/D clock to output pins, and FPGA input buffer add up to 9 to 16 ns, while the clock cycle time is 10 ns. So aligning the clock and data at the input latch is tricky.
Per the A/D data sheet, the value on the output pins is stable for about 5ns (minimum) and the FPGA data sheet says the latches need about 1ns to capture the value (setup+hold times from the clock edge). So we have a 4 ns window in which everything will work right.
It's hard to measure the actual offset at the internal latch input of the FPGA, so for initial setup I would like to be able to adjust the phasing of the A/D clock relative to the internal latch clock over the full 10 ns range.
First option is to use the built-in delays. The *.ucf file supports the per-pin specifications IFD_DELAY_VALUE and IBUF_DELAY_VALUE which put variable amounts of delay between the input pin and the logic (the former applies when using the latch built-in to the I/O Block, and the latter applies when the I/O Block is just used as a buffer). Total adjustment range is about 2 ns, which might be enough.
Next step up in complexity is to use the Digital Clock Module (DCM) to adjust the phase of the generated clock. The DCM can produce essentially any clock phase, but for this application, I think I can just use the 4-phase quadrature outputs. That gives me effectively 0 2.5, 5, 7.5 ns adjustment points, and combined with the IFD_DELAY_VALUE, I can get within 0.5 ns of any required timing offset.

HDMI Breakout Part 2

 I see the PCB in my Nov 6, 2013 post is getting some interest, so here's more info about it. The image to the left is a Kicad screenshot. The breakout connector (P1, CONN_5X2) is at the top, and pin 1 is the top right pad. Odd-numbered pins on top, and even-numbered on the bottom.
Top connections are:
1 Ground
3 HOTP-J
5 DCC_D-J1
7 DCC_C-J1
9 CEC-J1
and the bottom connections are:
2 +5V (J1 and J2 both)
4 HOTP-J2
6 DCC_D-J2
8 DCC_C-J2
10 CEC-J2

So to use the board as a passthrough connection, add jumpers connecting 3-4, 5-6, 7-8, and 9-10. Obviously, it's NOT a good idea to have a jumper connecting 1 and 2 (ground and +5V).

Here's the schematic. Pin 20 is the metal shell of the connector, not a real pin.

HDMI breakout PCB

This is probably only useful to a small handful of people, but if you're and engineer developing HDMI products that might include you.
For some work developing HDMI-compatible FPGA code, I needed to observe the control signals with a scope. So I built up this little breakout PCB. The high-speed video TMDS signals are routed directly through from one connector to the other. I tried to keep them equal length and as short as possible. Don't have any way to verify impedance and reflections, but it works ok on one TV with short HDMI cables.
The low speed (CEC, SCL, etc) signals are brought out to the header in the back in the photo. Jumpers allow the signals to pass through, or they can be disconnected to test and modify them.
The PCB is shared on OshPark. See http://oshpark.com/profiles/sensicomm  if you want to use this design. It uses standard HDMI female connectors, available from DigiKey and many other vendors. Soldering the fine-pitch surface mount pins on the connectors is a bit of a challenge. I tried soldering individual pins, but ended up using the flood it with solder and mop up the excess with solder-wick method.

Atlys and HDMI on Linux

Xilinx App Note 495 describes sample implementations of DVI/HDMI receiver and transmitter on the Digilent Atlys board. I built the code using WebPACK 12.4, and it works as advertised: The colorbar test pattern displays nicely on my HDMI monitor.

Also installed Digilent's Linux version of their Adept tools for FPGA programming. They don't seem to have the full GUI version available, but the command-line tool was able to load my test code (as a WebPACK-generated .bit file) into the Atlys FPGA with no problem. Don't see any way to load code into the SPI flash: it appears that Windows-based tools are still needed for that.

Only one minor glitch: I use Debian, which isn't one of Digilent's supported distributions. In recent versions of Debian, the udev package doesn't allow plugin devices to have protection mode 0666, which means that the Digilent tools will only work if run as root.
The fix is to edit "/etc/udev/rules.d/52-digilent-usb.rules" and add a group:
SYSFS{idVendor}=="1443", MODE="666" GROUP="plugdev"
then any user in the "plugdev" group can run the Digilent tools. The /etc/group file should have a line like
plugdev:x:46:jr
where "jr" is my username.

Digilent Atlys

For Christmas, Santa Claus brought a Digilent Atlys development board for the Xilinx Spartan-6 FPGA's. Nice board, with a bunch of peripherals (Ethernet, USB, audio, HDMI!, etc).
The HDMI interface and protocol is implemented as firmware in the FPGA. My only test so far was to connect an HDMI output to a monitor and power up the board. It generates a test pattern of colored squares right out of the box. Nice. 2011 is going to be interesting.
While setting it up, I also noticed that Digilent now provides tools for Linux programming and communication with their FPGA boards. Need to check those out as well.

Saltwater immersion testing

I've been working on a project that uses a custom A/D-FPGA board to generate and process sonar signals. Basic functionality is working, so the client took it to the dock for some live testing.
The testing included an "unscheduled" saltwater immersion experiment, with power applied to the board no less.
It was recovered after 24 hours; effects on the circuit were not beneficial.
So far, it looks as if the flash memory and A/D converters survived with just minor corrosion on the leads. The FPGA is interesting: definitely nonfunctional, and there's a pit where the epoxy case is crumbly. I suspect that the 1.2 volt switching regulator went out of range and fried the FPGA core.
Next time we plan to use a waterproof case.

MHZ100Q - on sourceforge

I can now digitize one signal at 100MHz using my A/D card, capture in the Digilent Xilinx FPGA board, and upload to a PC via the USB port. I'm using Octave to upload and display the data, making a sort of oscilloscope. So I decided it's time to create a sourceforge open-source project.
It's http://mhz100q.sourceforge.net . Code is all in Subversion. It's all there, but I still need to create some build instructions and other documentation.

Cypress CY7C68013A (FX2) USB to FPGA

I just got the USB interface working under Linux for the Digilent Nexys and Nexys 2 FPGA boards. Started with some ideas from the blog at braiden.org , updated the FX2 firmware and added from VHDL test code. Details at www.sensicomm.com/main/projects/fpga/ieee_fpga.shtml#nexys_usb .

Quad 100 MHz A/D PCB

The paying customers are taken care of for a while, so it's time to update the blog. I want to test some DSP on the FPGA (filters, RF signal modulation/demodulation, etc)., so I need A/D and D/A capability. I could buy a board, but it's more fun to build my own. So I settled on a quad, 8-bit, 100MHz board that interfaces to the Xilinx or Digilent board via the 100-pin FX/2 connector. The block diagram shows one of the 4 channels. As a test, I'm capturing a signal and displaying it on the VGA output. The signal is looking reasonable. More details on my website:
http://www.sensicomm.com/main/projects/fpga/quad_100mhz_a2d.shtml

FPGA frequency counter code.

An FPGA project that does something useful: implements a frequency counter using the Xilinx Spartan 3AN development board. Basically consists of two counters and the AX8 uC core. The first counter generates a 1 Hz timing signal from the on-board 50 MHz crystal oscillator, and the second counter counts the signal under test. The AX8 core runs a simple program that reads the count value and formats it for display on the LCD.
The attached image is counting the frequency of a VEX RC transmitter using a 75.97 MHz crystal. The measured count is 75.971459 MHz, which is within 0.002% of the expected value. The development board uses an xtal oscillator marked AGXO-751L 50.000 A. I found a datasheet at www.inysa.es indicating that A versions are 100ppm, or 0.01%, so the measured value is well inside the tolerances.
I'll be posting the code when I get it ready.

AX8 core, UART, and uC programming

Progress! I got the AX8 core (a uC based on the Atmel AVR instruction set, available from opencores.org) running on the Xilinx Spartan-3an eval board. It writes to the UART core, and I can see the UART's output on my PC.
Since it takes 7 minutes or more to recompile an FPGA design, I decided to set up data2mem. That's a Xilinx-supplied tool to update just the contents of internal RAM blocks without doing a full recompile. It took quite a bit of searching, but I figured out how to do it, and it works fast.
Details are online at
> www.sensicomm.com/main/projects/fpga/AX8_on_Xilinx.shtml

fpga uC core

For most things, I'll need a microcomputer core on the FPGA. Xilinx has the Microblaze and Picoblaze synthesizable cores, but I want something that's open-source. That way I can see how things are done and modify as desired.
There are several open cores available. I settled on the AX8 from opencores.org. It's fairly simple, but it implements most of the Atmel AVR instruction set (which I have a lot of experience with). A simple "Hello World" in this core turned out to be pretty straightforward.
After downloading AX8 from opencores, I loaded A90S1200.vhd, AX8.vhd, AX_TC8.vhd, and AX_Port.vhd into ISE WEBPACK. Then I modified A90S1200.vhd to divide the clock down to a lower frequency and to invert the reset line (since the core is set up for an active-low reset and most of the buttons on the board are active-high). I then created a .ucf file to attach port D to the LED's.
The test program just writes to port D to blink the LED's. I assemble the program with tavrasm, then convert the program to a rom vhdl file using the hex2rom program that's included with AX8.
And that's it!. Build in ISE, download to the FPGA, and the LED's blink.
I can post source if anybody's interested.

VHDL HelloWorld

First step is to write a "Hello World" program. This one just counts cycles of the input clock, and displays a binary count on the LED's. Sample code is included here. hello.vhd implements the counter and connects to the LED's. The ucf file defines the clock and LED connections on the board.These would need to be changed to use anything other than this specific Spartan 3AN development board.
It loads and the lights blink, so now we can do some real work.

-- $Id: hello.vhd,v 1.1 2008/05/01 15:18:18 jrothwei Exp $
-- Joseph Rothweiler, Sensicomm LLC Started 16Apr2008.
-- "Hello world" program. Count down the clock, and display a binary
-- count on the 8 LED's.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;      -- Common things.
use IEEE.STD_LOGIC_ARITH.ALL;     -- Makes the "div+1" instruction work.
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
 Port (
   CLK_50M : in  STD_LOGIC;  -- Input: 50 MHz clock.
   LED : out  STD_LOGIC_VECTOR (7 downto 0)
 );
end main;

architecture Behavioral of main is
 signal div: STD_LOGIC_VECTOR(29 downto 0);
begin
 process(CLK_50M) begin
   if rising_edge(CLK_50M) then
     div <= div+1;              -- Increment counter on every clock.
     LED <= div(29 downto 22);  -- Display the counter MSB's on the LED's.
     end if;   end process; end Behavioral;

# $Id: hello_3an.ucf,v 1.1 2008/05/01 15:23:01 jrothwei Exp $
# Joseph Rothweiler Sensicomm LLC started 01may2008.
# Settings for the Xilinx Spartan-3AN development board by Digilent.
# This file just contains the parts I'm using.

#################################################
# Settings specific to this Board.
CONFIG VCCAUX = "3.3" ;
CONFIG ENABLE_SUSPEND = "FILTERED" ;
CONFIG POST_CRC = "DISABLE" ;

#################################################
# The main onboard clock, with the recommended settings.

NET "CLK_50M"       LOC = "E12"  | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN  10.000 VALID 20.000 BEFORE "CLK_50M" ;
OFFSET = OUT 20.000 AFTER "CLK_50M" ;

#################################################
# The row of 8 LED's above the switches.

NET "LED<0>"        LOC = "R20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<1>"        LOC = "T19"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<2>"        LOC = "U20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<3>"        LOC = "U19"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<4>"        LOC = "V19"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<5>"        LOC = "V20"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<6>"        LOC = "Y22"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<7>"        LOC = "W21"  | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;

Starting FPGA project

I've just started working with the Xilinx Spartan-3AN development board. First step was getting the USB interface to work with my Debian 32-bit Linux system. Fortunately, the latest (10.1) version of the Xilinx ISE WebPACK software supports a nice interface using the libusb package. Notes on the system are now on my website, at www.sensicomm.com/main/projects/fpga/ieee_fpga.shtml