Friday, May 23, 2008

AX8 core, UART, and uC programming

Progress! I got the AX8 core (a uC based on the Atmel AVR instruction set, available from opencores.org) running on the Xilinx Spartan-3an eval board. It writes to the UART core, and I can see the UART's output on my PC.
Since it takes 7 minutes or more to recompile an FPGA design, I decided to set up data2mem. That's a Xilinx-supplied tool to update just the contents of internal RAM blocks without doing a full recompile. It took quite a bit of searching, but I figured out how to do it, and it works fast.
Details are online at
> www.sensicomm.com/main/projects/fpga/AX8_on_Xilinx.shtml

Thursday, May 22, 2008

Page Counter for this blog

I decided to add a page counter, to see if anybody's actually reading my blog. There are lots around, but I wanted something simple. I have a personal page with Verizon, so I decided to use one of their page counters. Turned out to be pretty easy:
First, I created file counter_blog.html on my Verizon-hosted page which is just:
<html><head></head><body>*** code to make a counter***</body></html>
Where the body is just an image tag. Details are from the service provider.
Now, to put it on this blog, I just used the "add html" option under "layout" on the dashboard, and added an iframe like this:
<iframe src="http://mysite.example.com/counter_blog.html" width=180 height=40></iframe>
And that's it. Happy reading.

Saturday, May 3, 2008

fpga uC core

For most things, I'll need a microcomputer core on the FPGA. Xilinx has the Microblaze and Picoblaze synthesizable cores, but I want something that's open-source. That way I can see how things are done and modify as desired.
There are several open cores available. I settled on the AX8 from opencores.org. It's fairly simple, but it implements most of the Atmel AVR instruction set (which I have a lot of experience with). A simple "Hello World" in this core turned out to be pretty straightforward.
After downloading AX8 from opencores, I loaded A90S1200.vhd, AX8.vhd, AX_TC8.vhd, and AX_Port.vhd into ISE WEBPACK. Then I modified A90S1200.vhd to divide the clock down to a lower frequency and to invert the reset line (since the core is set up for an active-low reset and most of the buttons on the board are active-high). I then created a .ucf file to attach port D to the LED's.
The test program just writes to port D to blink the LED's. I assemble the program with tavrasm, then convert the program to a rom vhdl file using the hex2rom program that's included with AX8.
And that's it!. Build in ISE, download to the FPGA, and the LED's blink.
I can post source if anybody's interested.

Thursday, May 1, 2008

VHDL HelloWorld

First step is to write a "Hello World" program. This one just counts cycles of the input clock, and displays a binary count on the LED's. Sample code is included here. hello.vhd implements the counter and connects to the LED's. The ucf file defines the clock and LED connections on the board.These would need to be changed to use anything other than this specific Spartan 3AN development board.
It loads and the lights blink, so now we can do some real work.


-- $Id: hello.vhd,v 1.1 2008/05/01 15:18:18 jrothwei Exp $
-- Joseph Rothweiler, Sensicomm LLC Started 16Apr2008.
-- "Hello world" program. Count down the clock, and display a binary
-- count on the 8 LED's.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL; -- Common things.
use IEEE.STD_LOGIC_ARITH.ALL; -- Makes the "div+1" instruction work.
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity main is
Port (
CLK_50M : in STD_LOGIC; -- Input: 50 MHz clock.
LED : out STD_LOGIC_VECTOR (7 downto 0)
);
end main;

architecture Behavioral of main is
signal div: STD_LOGIC_VECTOR(29 downto 0);
begin
process(CLK_50M) begin
if rising_edge(CLK_50M) then
div <= div+1; -- Increment counter on every clock.
LED <= div(29 downto 22); -- Display the counter MSB's on the LED's.
end if; end process; end Behavioral;



# $Id: hello_3an.ucf,v 1.1 2008/05/01 15:23:01 jrothwei Exp $
# Joseph Rothweiler Sensicomm LLC started 01may2008.
# Settings for the Xilinx Spartan-3AN development board by Digilent.
# This file just contains the parts I'm using.

#################################################
# Settings specific to this Board.
CONFIG VCCAUX = "3.3" ;
CONFIG ENABLE_SUSPEND = "FILTERED" ;
CONFIG POST_CRC = "DISABLE" ;

#################################################
# The main onboard clock, with the recommended settings.

NET "CLK_50M" LOC = "E12" | IOSTANDARD = LVCMOS33 | PERIOD = 20.000 ;
OFFSET = IN 10.000 VALID 20.000 BEFORE "CLK_50M" ;
OFFSET = OUT 20.000 AFTER "CLK_50M" ;

#################################################
# The row of 8 LED's above the switches.

NET "LED<0>" LOC = "R20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<1>" LOC = "T19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<2>" LOC = "U20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<3>" LOC = "U19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<4>" LOC = "V19" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<5>" LOC = "V20" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<6>" LOC = "Y22" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;
NET "LED<7>" LOC = "W21" | IOSTANDARD = LVCMOS33 | DRIVE = 8 | SLEW = SLOW ;