Xilinx Spartan-3 I/O timing

Working on updating the MHZ100Q project, and one significant design issue is I/O delay. To review, the Xilinx Spartan-3A FPGA generates a 100MHz clock using an internal DCM block, and this clock drives an external 100MHz A/D converter. The total delays through the output buffer, A/D clock to output pins, and FPGA input buffer add up to 9 to 16 ns, while the clock cycle time is 10 ns. So aligning the clock and data at the input latch is tricky.
Per the A/D data sheet, the value on the output pins is stable for about 5ns (minimum) and the FPGA data sheet says the latches need about 1ns to capture the value (setup+hold times from the clock edge). So we have a 4 ns window in which everything will work right.
It's hard to measure the actual offset at the internal latch input of the FPGA, so for initial setup I would like to be able to adjust the phasing of the A/D clock relative to the internal latch clock over the full 10 ns range.
First option is to use the built-in delays. The *.ucf file supports the per-pin specifications IFD_DELAY_VALUE and IBUF_DELAY_VALUE which put variable amounts of delay between the input pin and the logic (the former applies when using the latch built-in to the I/O Block, and the latter applies when the I/O Block is just used as a buffer). Total adjustment range is about 2 ns, which might be enough.
Next step up in complexity is to use the Digital Clock Module (DCM) to adjust the phase of the generated clock. The DCM can produce essentially any clock phase, but for this application, I think I can just use the 4-phase quadrature outputs. That gives me effectively 0 2.5, 5, 7.5 ns adjustment points, and combined with the IFD_DELAY_VALUE, I can get within 0.5 ns of any required timing offset.

915MHz signal with a 100MHz A/D

I've been using a Radiotronix DP-1205 RF transceiver that operates in the 915MHz unlicensed ISM band. The power level, operating frequency, FM deviation, etc., are set using the SPI serial interface. So I decided to see if my MHZ100Q A/D PCB could see the signal. I bypassed the antialiasing filter and associated buffer, and then coupled the transceiver signal to the input.
It Works! The signal is low amplitude (less than 10% of full scale), and there are a lot of spurs 20dB down or so, but the carrier is clearly visible. The 902 to 928 MHz band is being undersampled at 100 MHZ so it shows up at 2 to 28 MHz in the digitized signal (in full compliance with Nyquist's rules).
The A/D is only spec'ed to 550 MHz, so I wouldn't trust the signal and distortion levels, but it's definitely a usable signal.
More details on the MHZ100Q project site at Source Forge.

MHZ100Q - on sourceforge

I can now digitize one signal at 100MHz using my A/D card, capture in the Digilent Xilinx FPGA board, and upload to a PC via the USB port. I'm using Octave to upload and display the data, making a sort of oscilloscope. So I decided it's time to create a sourceforge open-source project.
It's http://mhz100q.sourceforge.net . Code is all in Subversion. It's all there, but I still need to create some build instructions and other documentation.

Quad 100 MHz A/D PCB

The paying customers are taken care of for a while, so it's time to update the blog. I want to test some DSP on the FPGA (filters, RF signal modulation/demodulation, etc)., so I need A/D and D/A capability. I could buy a board, but it's more fun to build my own. So I settled on a quad, 8-bit, 100MHz board that interfaces to the Xilinx or Digilent board via the 100-pin FX/2 connector. The block diagram shows one of the 4 channels. As a test, I'm capturing a signal and displaying it on the VGA output. The signal is looking reasonable. More details on my website:
http://www.sensicomm.com/main/projects/fpga/quad_100mhz_a2d.shtml